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  ? semiconductor components industries, llc, 2011 june, 2011 ? rev. 6 1 publication order number: mc74hct541a/d mc74hct541a octal 3-state non-inverting buffer/line driver/ line receiver with lsttl-compatible inputs high ? performance silicon ? gate cmos the mc74hct541a is identical in pinout to the ls541. this device may be used as a level converter for interfacing ttl or nmos outputs to high speed cmos inputs. the hct541a is an octal non ? inverting buffer/line driver/line receiver designed to be used with 3 ? state memory address drivers, clock drivers, and other bus ? oriented systems. this device features inputs and outputs on opposite sides of the package and two anded active ? low output enables. features ? output drive capability: 15 lsttl loads ? ttl/nmos ? compatible input levels ? outputs directly interface to cmos, nmos and ttl ? operating voltage range: 4.5 to 5.5 v ? low input current: 1  a ? in compliance with the jedec standard no. 7 a requirements ? chip complexity: 134 fets or 33.5 equivalent gates ? these devices are pb ? free and are rohs compliant 18 y1 2 a1 17 y2 3 a2 16 y3 4 a3 15 y4 5 a4 14 y5 6 a5 13 y6 7 a6 12 y7 8 a7 11 y8 9 a8 oe1 oe2 1 19 output enables data inputs non-inverting outputs pin 20 = v cc pin 10 = gnd logic diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information 20 1 1 20 marking diagrams soic ? 20 dw suffix case 751d hct541a awlyywwg hct 541a alyw   tssop ? 20 dt suffix case 948e soeiaj ? 20 f suffix case 967 74hct541a awlywwg 1 1 1 20 1 20 20 20 pdip ? 20 n suffix case 738 1 20 mc74hct541an awlyywwg 1 20 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or  = pb ? free package (note: microdot may be in either location)
mc74hct541a http://onsemi.com 2 pinout: 20 ? lead packages 19 20 18 17 16 15 14 2 1 34567 v cc 13 8 12 9 11 10 oe2 y1 y2 y3 y4 y5 y6 y7 y8 oe1 a1 a2 a3 a4 a5 a6 a7 a8 gnd l l h x l l x h l h x x function table inputs output y oe1 oe2 a l h z z z = high impedance x = don?t care (top view) ??????????????????????? maximum ratings ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? v cc ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? 20 ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? 35 ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? 75 ?? ?? ???? ???? ???? ?????????????? ?????????????? ?????????????? ?????? ?????? ?????? ?? ?? ?? ???? ???? ?????????????? ?????????????? ?????? ?????? ?? ??  c ???? ???? ???? ?????????????? ?????????????? ?????????????? ?????? ?????? ?????? ?? ?? ??  c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recom mended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. ?derating ? plastic dip: ? 10 mw/  c from 65  to 125  c soic package: ? 7 mw/  c from 65  to 125  c recommended operating conditions ???? ???? ?????????????? ?????????????? ??? ??? ???? ???? ?? ?? ???? ???? v cc ?????????????? ?????????????? ??? ??? ???? ???? ?? ?? ???? ???? ?????????????? ?????????????? ??? ??? ???? ???? ?? ?? ???? ???? ?????????????? ?????????????? ??? ??? ???? ???? ?? ??  c ???? ???? ?????????????? ?????????????? ??? ??? ???? ???? ?? ?? ? impedance circuit. for proper operation, v in and v out should be constrained to the range gnd  (v in or v out )  v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hct541a http://onsemi.com 3 dc characteristics (voltages referenced to gnd) v cc v guaranteed limit symbol parameter condition ? 55 to 25 c 85 c 125 c unit v ih minimum high ? level input voltage v out = 0.1v or v cc ? 0.1v |i out | 20  a 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 v v il maximum low ? level input voltage v out = 0.1v or v cc ? 0.1v |i out | 20  a 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 v v oh minimum high ? level output voltage v in = v ih or v il |i out | 20  a 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 v v in = v ih or v il |i out | 6.0ma 4.5 3.98 3.84 3.70 v ol maximum low ? level output voltage v in = v ih or v il |i out | 20  a 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 6.0ma 4.5 0.26 0.33 0.40 i in maximum input leakage current v in = v cc or gnd 5.5 0.1 1.0 1.0  a i oz maximum 3 ? state leakage current output in high impedance state v in = v il or v ih v out = v cc or gnd 5.5 0.5 5.0 10.0  a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0  a 5.5 4 40 160  a  i cc additional quiescent supply current v in = 2.4v, any one input v in = v cc or gnd, other inputs i out = 0  a 5.5 ? 55 c 25 to 125 c ma 2.9 2.4 1. total supply current = i cc +  i cc . ac characteristics (v cc = 5.0v, c l = 50 pf, input t r = t f = 6 ns) guaranteed limit symbol parameter ? 55 to 25 c 85 c 125 c unit t plh , t phl maximum propagation delay, input a to output y (figures 1 and 3) 23 28 32 ns t plz , t phz maximum propagation delay, output enable to output y (figures 2 and 4) 30 34 38 ns t pzl , t pzh maximum propagation delay, output enable to output y (figures 2 and 4) 30 34 38 ns t tlh , t thl maximum output transition time, any output (figures 1 and 3) 12 15 18 ns c in maximum input capacitance 10 10 10 pf c out maximum 3 ? state output capacitance (output in high impedance state) 15 15 15 pf c pd power dissipation capacitance (per buffer)* typical @ 25 c, v cc = 5.0 v pf 55 * used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hct541a http://onsemi.com 4 figure 1. c l * *includes all probe and jig capacitance test point oe1 or oe2 1.3v 3.0v gnd output y t pzl output y t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 1.3v 1.3v figure 2. switching waveforms device under test output test circuits figure 3. figure 4. c l * *includes all probe and jig capacitance test point device under test output 1k  connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 3.0v gnd input a output y t plh t phl 90% 1.3v 10% t r t tlh t f t thl 90% 1.3v 10% 1.3v
mc74hct541a http://onsemi.com 5 pin descriptions inputs a1, a2, a3, a4, a5, a6, a7, a8 (pins 2, 3, 4, 5, 6, 7, 8, 9) ? data input pins. data on these pins appear in non ? inverted form on the corresponding y outputs, when the outputs are enabled. controls oe1, oe2 (pins 1, 19) ? output enables (active ? low). when a low voltage is applied to both of these pins, the outputs are enabled and the device functions as a non ? inverting buffer. when a high voltage is applied to either input, the outputs assume the high impedance state. outputs y1, y2, y3, y4, y5, y6, y7, y8 (pins 18, 17, 16, 15, 14, 13, 12, 11) ? device outputs. depending upon the state of the output enable pins, these outputs are either non ? inverting outputs or high ? impedance outputs. logic detail v cc to 7 other buf- fers one of eight buffers input a oe1 oe2 output y ordering information device package shipping ? mc74hct541ang pdip ? 20 (pb ? free) 18 units / rail mc74hct541adwg soic ? 20 (pb ? free) 38 units / rail mc74hct541adwr2g soic ? 20 (pb ? free) 1000 / tape & reel MC74HCT541ADTR2G tssop ? 20* 2500 / tape & reel mc74hct541afg soeiaj ? 20 (pb ? free) 40 units / rail mc74hct541afelg soeiaj ? 20 (pb ? free) 2000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *these packages are inherently pb ? free.
mc74hct541a http://onsemi.com 6 package dimensions pdip ? 20 n suffix case 738 ? 03 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040   e 1.27 1.77 0.050 0.070 1 11 10 20 ? a ? seating plane k n f g d 20 pl ? t ? m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc soic ? 20 dw suffix case 751d ? 05 issue g 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane  h x 45  e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90  0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition. 
mc74hct541a http://onsemi.com 7 package dimensions tssop ? 20 dt suffix case 948e ? 02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8  notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . 110 11 20 pin 1 ident a b ? t ? 0.100 (0.004) c d g h section n ? n k k1 jj1 n n m f ? w ? seating plane ? v ? ? u ? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint
mc74hct541a http://onsemi.com 8 package dimensions soeiaj ? 20 f suffix case 967 ? 01 issue a dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.15 0.25 0.006 0.010 12.35 12.80 0.486 0.504 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.81 --- 0.032 a 1 h e q 1 l e  10  0  10  notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). h e a 1 l e q 1  c a z d e 20 110 11 b m 0.13 (0.005) e 0.10 (0.004) view p detail p m l a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mc74hct541a/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative


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